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VisualDSP++ Configurator
VisualDSP++ Configurator
VisualDSP++ requires a description of the platform (JTAG chain). The
platform definition is necessary for VisualDSP++ to communicate with
the hardware through the emulator.
The VisualDSP++ Configurator and ICE Test utilities allow configuration
and testing of the emulator hardware. ICE Test provides emulator detec-
tion and JTAG interface testing. Use the ICE Test to test the target. If
errors are encountered, they are reported immediately and the test ends.
Refer to VisualDSP++ online Help for information about the
VisualDSP++ Configurator and the ICE Test utility
JTAG Frequency
? If prevent the emulator from relation is not followed, processor. failures may
The ICE-100B emulator supports JTAG clock operation at 5 MHz. There
is a relationship between the JTAG frequency and the core clock fre-
quency of the processor. The core clock should be at least twice the JTAG
frequency in order for the JTAG interface to operate properly. On newer
Analog Devices processors, the core clock is a variable that is sometimes
set by switches or by software.
the core/JTAG clock scan
connecting to the
1-8
ICE-100B Emulator User Guide ?
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